The present invention is related to switched capacitor circuits. More particularly, the present invention is related to sigma-delta converters.
A number of electronic systems rely upon circuits that convert between the analog and digital domain. For example, cellular telephones typically include both an analog to digital converter and a digital to analog converter. The aforementioned converters are often implemented as sigma-delta modulators because of the favorable trade-off between power consumption, over-sampling rate (OSR), and signal to noise ratio (SNR) offered by sigma-delta modulators.
Existing systems have attempted to increase SNR provided by such sigma-delta modulators by increasing the effective sampling rate of the modulators. The following equation describes the increase in SNR achieved by doubling the effective sampling rate:Δ(SNR)=3(2n+1) dB, where n represents the order of a sigma-delta modulator.Thus, for example, by doubling the effective sampling rate the SNR is increased by fifteen dB where the sigma-delta modulator is a second order loop. This increase in effective sampling rate is typically achieved by providing two sampling capacitors operating with interleaved clock signals. An exemplary, conventional double-sampled digital to analog converter (DAC) 100 using two sampling capacitors is depicted in FIG. 1.
DAC 100 includes a first switched capacitor block 120 and a second switched capacitor block 130. Switched capacitor block 120 includes switches 121–126 along with switches SA, SB; and switched capacitor block 130 includes switches 131–136 along with switches SA, SB. As shown, the conventional architecture utilizes two sampling capacitors for each switched capacitor block. Thus, switched capacitor block 120 includes a capacitor bank 111 with sampling capacitors (CD1) 112, 114. Similarly, switched capacitor block 130 includes a capacitor bank 115 with sampling capacitors (CD2) 116, 118. In operation, switches 121, 123, 124, 126, 132, 135 close during a first phase (P1), and switches 122, 125, 131, 133, 134, 136 close during a second phase (P2). Thus, sampling capacitors 116, 118 of switched capacitor block 130 charge during P2. At the same time, charge is transferred from sampling capacitors 112, 114 to integration capacitors (Cu) 140. During the opposite phase, P1, sampling capacitors 116, 118 are charged, and charge is transferred from sampling capacitors 112, 114 to integration capacitors 140. By charging and transferring during two phases, the effective sampling rate of DAC 100 is doubled.
While the SNR is increased due to the increased sampling rate, doubling the effective sampling rate by use of two sampling capacitors operating with interleaved clock signals typically produces a phase-dependent gain error due to a mismatch between sampling capacitors (CD1) 112, 114 and sampling capacitors (CD2) 116, 118. This phase-dependent gain error is referred to herein as an alternating gain effect that causes quantization noise to fold over into the signal bandwidth. In particular, as described by the following equations, charge transferred to integration capacitors 140 during P1 is different from that transferred during P2:QP2=(Vrefp−Vrefm)CD1 QP1=(Vrefp−Vrefm)CD2 Thus, where CD1=CD2+ΔC, the charge difference between phases is (Vrefp−Vrefm) ΔC. This charge difference results in the alternating gain effect noted above.
One solution for limiting the alternating gain effect is to increase the size of sampling capacitors 112, 114, 116, 118. By doing so, any difference (ΔC) between sampling the first set of sampling capacitors 112, 114 and the second set of sampling capacitors 116, 118 is rendered insignificant. This approach, however, is costly in terms of area and other design considerations.
Another approach for dealing with the alternating gain effect is to use floating capacitor design. An example of such a floating design is set forth in “Low-Voltage Double-Sampled ΣΔ Converters”, IEEE Journal of Solid State Circuits, Vol. 32, No. 12, pp. 1907–1919, Dec. 12, 1997. However, in such designs the transfer function is changed from that of a conventional double-sampled sigma-delta circuit. In some cases this change in transfer function is not significant for a second order filter, but becomes increasingly significant for higher order filters.
Hence, for at least the aforementioned reasons, there exists a need in the art for advanced circuits, systems and methods for implementing double-sampled delta sigma modulators.